The present invention relates to a semiconductor device and a manufacturing method thereof and particularly relates to the techniques which are effective when applied to a semiconductor device using an SOI (Silicon On Insulator) substrate and a manufacturing method thereof.
As a semiconductor device capable of suppressing short-channel characteristics and suppressing element variations, today, a semiconductor device using an SOI substrate is used. The SOI substrate is a substrate in which a BOX (Buried Oxide) film (buried oxide film) is formed on a supporting substrate formed of, for example, high-resistance Si (silicon), and a thin layer (silicon layer, SOI layer) mainly containing Si (silicon) is formed on the BOX film. When MISFETs (Metal Insulator Semiconductor Field Effect Transistors: MIS-type field-effect transistors) are formed on the SOI substrate, short-channel characteristics can be suppressed without doping an impurity into a channel layer. As a result, mobility can be improved, and element variations caused by impurity fluctuation can be improved. Therefore, when a semiconductor device is manufactured by the SOI substrate, improvement in the integration density and operation speed of the semiconductor device and improvement in operation margins by variation reduction can be expected.
Japanese Patent Application Laid-Open Publication No. 2006-190821 (Patent Document 1) describes that source/drain regions of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) on a silicon substrate are formed by a first epitaxial growth layer and a second epitaxial growth layer, the second epitaxial growth layer being formed so as to run on an isolation region.
Japanese Patent Application Laid-Open Publication No. 2006-190823 (Patent Document 2) describes a structure in which an epitaxial growth layer constituting source/drain regions of a MOSFET on a silicon substrate is formed so as to be placed on an isolation region.
Japanese Patent Application Laid-Open Publication No. 2009-094369 (Patent Document 3) describes providing an SOI region and a bulk region on a silicon substrate and forming MISFETs in the regions.
Japanese Patent Application Laid-Open Publication No. 2008-270473 (Patent Document 4) describes forming an SRAM (Static Random Access Memory) on an SOI substrate.